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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MC9S08FL16 Rev. 2, 7/2009
MC9S08FL16 Series
Covers: MC9S08FL16 and MC9S08FL8
MC9S08FL16
32-Pin LQFP 873A-03 32-Pin SDIP 1376-02
Features:
8-Bit S08 Central Processor Unit (CPU)
* Up to 20 MHz CPU at 4.5 V to 5.5 V across temperature range of -40 C to 85 C * HC08 instruction set with added BGND instruction * Support for up to 32 interrupt/reset sources
* Illegal address detection with reset * Flash block protection
Development Support
* Single-wire background debug interface * Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints). * On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes.
On-Chip Memory
* Up to 16 KB flash read/program/erase over full operating voltage and temperature * Up to 1024-byte random-access memory (RAM) * Security circuitry to prevent unauthorized access to RAM and flash contents
Peripherals
* IPC -- Interrupt priority controller to provide hardware based nested interrupt mechanism * ADC -- 12-channel, 8-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop; optional hardware trigger; fully functional from 4.5 V to 5.5 V * TPM -- One 4-channel and one 2-channel timer/pulse-width modulators (TPM) modules; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel * MTIM16 -- One 16-bit modulo timer with optional prescaler * SCI -- One serial communications interface module with optional 13-bit break; LIN extensions
Power-Saving Modes
* Two low power stop modes; reduced power wait mode * Allows clocks to remain enabled to specific peripherals in stop3 mode
Clock Source Options
* Oscillator (XOSC) -- Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 1 MHz to 16 MHz * Internal Clock Source (ICS) -- Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies up to 10 MHz
Input/Output
* 30 GPIOs including 1 output-only pin and 1 input-only pin
System Protection
* Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock * Low-voltage detectionwith reset or interrupt; selectable trip points * Illegal opcode detection with reset
Package Options
* 32-pin SDIP * 32-pin LQFP
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1 2 3 4 5 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 System Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9 5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9 5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 10 5.5 ESD Protection and Latch-Up Immunity . . . . . . 11 5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 Supply Current Characteristics . . . . . . . . . . . . . 17 5.8 External Oscillator (XOSC) and ICS Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 5.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . 5.9.2 TPM Module Timing . . . . . . . . . . . . . . . . 5.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 5.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . 5.12 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 5.12.1Radiated Emissions . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . 5.9 19 21 22 23 24 26 27 27 27 28 28
6 7
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev 1 2 Date March 18, 2009 July 20, 2009 Initial public release. Updated Section 5.12, "EMC Performance." and corrected Figure 1 and Table 1. Corrected default trim value to 31.25 kHz. Description of Changes
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08FL16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
MC9S08FL16 Series Data Sheet, Rev. 2 2 Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of MC9S08FL16 series MCU.
PTA0/ADP0 16-BIT MODULO TIMER HCS08 CORE (MTIM16) TCLK PTA1/ADP1 PTA2/ADP2 CPU BDC 2-CH TIMER/PWM MODULE (TPM2) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP IRQ LVD INTERRUPT PRIORITY CONTROLLER (IPC) PTB0/RxD/ADP4 PTB1/TxD/ADP5 SERIAL COMMUNICATIONS INTERFACE (SCI) USER FLASH MC9S08FL16 -- 16,384 BYTES MC9S08FL8 -- 8,192 BYTES 4-CH TIMER/PWM USER RAM MC9S08FL16 -- 1,024 BYTES MC9S08FL8 -- 768 BYTES MODULE (TPM1) TPM1CH[3:0] TxD RxD PTB2/ADP6 TPM2CH[1:0]
PORT A
PTA3/ADP3 PTA4/BKGD/MS PTA5/IRQ/TCLK/RESET
RESET IRQ
PTA6/TPM2CH0 PTA7/TPM2CH1
ON-CHIP ICE AND DEBUG MODUE (DBG)
PORT B
PTB3/ADP7 PTB4/TPM1CH0 PTB5/TPM1CH1 PTB6/XTAL PTB7/EXTAL
20 MHz INTERNAL CLOCK SOURCE (ICS) EXTAL XTAL
PTC0/ADP8 PTC1/ADP9 PTC2/ADP10
EXTERNAL OSCILLATOR SOURCE (XOSC)
PORT C
PTC3/ADP11 PTC4 PTC5
VDD VSS VOLTAGE REGULATOR
PTC6 PTC7 12-CH 8-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) ADP[11:0] PTD0 PTD1
VREFH VREFL VDDA VSSA
PORT D
PTD2/TPM1CH2 PTD3/TPM1CH3 PTD4 PTD5
NOTE 1. PTA4 is output only when used as port pin. 2. PTA5 is input only when used as port pin.
Figure 1. MC9S08FL16 Series Block Diagram
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 3
System Clock Distribution
2
System Clock Distribution
MC9S08FL16 series use ICS module as clock sources. The ICS module can use internal or external clock source as reference to provide up to 20 MHz CPU clock. The output of ICS module includes, * OSCOUT -- XOSC output provides external reference clock to ADC. * ICSFFCLK -- ICS fixed frequency clock reference (around 32.768 kHz) provides double of the fixed lock signal to TPMs and MTIM16. * ICSOUT -- ICS CPU clock provides double of the bus clock which is basic clock reference of peripherals. * ICSLCLK -- Alternate BDC clock provides debug signal to BDC module. The TCLK pin is an extra external clock source. When TCLK is enabled, it can provide alternate clock source to TPMs and MTIM16. The on-chip 1 kHz clock provides clock source of COP module.
TCLK 1 kHz
COP
TPM1
TPM2
MTIM16
ADC
OSCOUT
ICSFFCLK ICS ICSOUT
/2
FIXED CLOCK (XCLK)
/2
BUS CLOCK
ICSLCLK
XOSC CPU EXTAL XTAL SCI BDC FLASH RAM IPC
Figure 2. System Clock Distribution Diagram
MC9S08FL16 Series Data Sheet, Rev. 2 4 Freescale Semiconductor
Pin Assignments
3
Pin Assignments
This section shows the pin assignments for the MC9S08FL16 series devices.
PTC5 PTC4 PTA5/IRQ/TCLK/RESET PTD2/TPM1CH2 PTA4/BKGD/MS PTD0 PTD1 VDD VSS PTB7/EXTAL PTB6/XTAL PTB5/TPM2CH1 PTD3/TPM1CH3 PTB4/TPM1CH0 PTC3/ADP11 PTC2/ADP10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
PTC6 PTC7 PTA0/ADP0 PTD5 PTA1/ADP1 PTA2/ADP2 PTA3/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/RxD/ADP4 PTB1/TxD/ADP5 PTB2/ADP6 PTD4 PTB3/ADP7 PTC0/ADP8 PTC1/ADP9
Figure 3. MC9S08FL16 Series 32-Pin SDIP Package
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 5
Pin Assignments
PTA5/IRQ/TCLK/RESET
PTD2/TPM1CH2
PTA0/ADP0
26
PTC4
PTC5
PTC6
PTC7
32
31
30
29
28
27
25 PTD5
PTA4/BKGD/MS 1 PTD0 PTD1 VDD VSS PTB7/EXTAL PTB6/XTAL PTB5/TPM1CH1
2 3 4 5 6 7 8 10 11 12 13 14 15 16
24 23 22 21 20 19 18
PTA1/ADP1 PTA2/ADP2 PTA3/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/RxD/ADP4 PTB1/TxD/ADP5
17 PTB2/ADP6
PTD3/TPM1CH3 9
PTB4/TPM1CH0
PTC1/ADP9
PTC0/ADP8
PTB3/ADP7
PTC3/ADP11
Figure 4. MC9S08FL16 Series 32-Pin LQFP Package Table 1. Pin Availability by Package Pin-Count
Pin Number 32-SDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32-LQFP 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 PTB7 PTB6 PTB5 PTD3 PTB4 PTC3 I/O I/O I/O I/O I/O I/O EXTAL XTAL I O TPM1CH1 I/O TPM1CH3 I/O TPM1CH0 I/O ADP11 I Port Pin PTC5 PTC4 PTA5 PTD2 PTA4 PTD0 PTD1 I/O I/O I/O I I/O O I/O I/O VDD VSS I I IRQ I TCLK BKGD I I RESET MS I I TPM1CH2 I/O <-- Lowest Alt 1 Priority I/O --> Highest Alt 2 I/O Alt 3 I/O
MC9S08FL16 Series Data Sheet, Rev. 2 6 Freescale Semiconductor
PTC2/ADP10
PTD4
Pin Assignments
Table 1. Pin Availability by Package Pin-Count (continued)
Pin Number 32-SDIP 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 32-LQFP 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Port Pin PTC2 PTC1 PTC0 PTB3 PTD4 PTB2 PTB1 PTB0 PTA7 PTA6 PTA3 PTA2 PTA1 PTD5 PTA0 PTC7 PTC6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ADP0 I ADP6 TxD RxD I I/O I ADP5 ADP4 I I <-- Lowest Alt 1 Priority I/O --> Highest Alt 2 ADP10 ADP9 ADP8 ADP7 I/O I I I I Alt 3 I/O
TPM2CH1 I/O TPM2CH0 I/O ADP3 ADP2 ADP1 I I I
NOTE When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software must clear out any associated flags before interrupts are enabled. Table 1 illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. Disable all modules that share a pin before enabling another module.
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 7
Memory Map
4
Memory Map
Figure 5 shows the memory map for the MC9S08FL16 series. On-chip memory in the MC9S08FL16 series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into two groups: * Direct-page registers (0x0000 through 0x003F) * High-page registers (0x1800 through 0x187F)
$0000 DIRECT PAGE REGISTERS $003F $0040 $033F $0340 RAM 768 BYTES $003F $0040 RAM 1024 BYTES $043F $0440 UNIMPLEMENTED UNIMPLEMENTED $0000 DIRECT PAGE REGISTERS
$17FF $1800 $187F $1880
HIGH PAGE REGISTERS
$17FF $1800 $187F $1880
HIGH PAGE REGISTERS
UNIMPLEMENTED
UNIMPLEMENTED $BFFF $C000
$DFFF $E000 FLASH 8192 BYTES $FFFF $FFFF
FLASH 16384 BYTES
MC9S08FL8 Figure 5. MC9S08FL16 Series Memory Map
MC9S08FL16
MC9S08FL16 Series Data Sheet, Rev. 2 8 Freescale Semiconductor
Electrical Characteristics
5
5.1
Electrical Characteristics
Introduction
This section contains electrical and timing specifications for the MC9S08FL16 series of microcontrollers available at the time of publication.
5.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
T
D
NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate.
5.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled.
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 9
Electrical Characteristics
Table 3. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value -0.3 to 5.8 120 -0.3 to VDD + 0.3 25 -55 to 150
Unit V mA V mA C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
5.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 4. Thermal Characteristics
Rating Operating temperature range (packaged) Thermal resistance Single-layer board 32-pin SDIP 32-pin LQFP Thermal resistance Four-layer board 32-pin SDIP 32-pin LQFP JA 35 56 C/W JA 60 85 C/W Symbol TA Value TL to TH -40 to 85 Unit C
The average chip-junction temperature (TJ) in C can be obtained from:
MC9S08FL16 Series Data Sheet, Rev. 2 10 Freescale Semiconductor
Electrical Characteristics
TJ = TA + (PD x JA)
Eqn. 1
where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O far much smaller than Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is:
PD = K / (TJ + 273 C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD x (TA + 273 C) + JA x (PD)2 Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
5.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. During the device qualification, ESD stresses were performed for the human body model (HBM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification.
Table 5. ESD and Latch-Up Test Conditions Model
Human body
Description
Series resistance Storage capacitance Number of pulses per pin Minimum input voltage limit
Symbol
R1 C -- -- --
Value
1500 100 3 -2.5 7.5
Unit
pF -- V V
Latch-up Maximum input voltage limit
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 11
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics No.
1 2 3
1
Rating1
Human body model (HBM) Charge device model (CDM) Latch-up current at TA = 85 C
Symbol
VHBM VCDM ILAT
Min
2000 500 100
Max
-- -- --
Unit
V V mA
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.
5.6
DC Characteristics
Table 7. DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Num C 1 Characteristic Symbol -- All I/O pins, low-drive strength All I/O pins, high-drive strength Max total IOH for all ports All I/O pins, low-drive strength All I/O pins, high-drive strength Max total IOL for all ports All digital inputs All digital inputs All digital inputs All input only pins (per pin) Condition -- ILoad = -2 mA VOH ILoad = -10 mA IOHT -- ILoad = 2 mA VOL ILoad = 10 mA IOLT VIH VIL Vhys |IIn| -- -- -- -- -- -- 0.65 x VDD -- 0.06 x VDD -- -- -- -- -- -- 1.5 100 -- 0.35 x VDD -- mA V V mV A VDD - 1.5 -- -- -- -- -- -- 100 1.5 V mA Min. 4.5 VDD - 1.5 Typical1 -- -- Max. 5.5 -- V Unit V
P Operating voltage C Output high voltage Output high current Output low voltage Output low current Input high voltage Input low voltage Input hysteresis
2 P D C 4 P 5 6 7 8 D P P C
3
9
Input P leakage current Hi-Z (off-state) P leakage current Pullup, C pulldown resistors Pullup, C pulldown resistors
VIn = VDD or VSS
0.1
1
10
All input/output (per pin) All digital inputs, when enabled (all I/O pins other than PTA5/IRQ/TCLK/RESET) (PTA5/IRQ/TCLK/RESET)
|IOZ|
VIn = VDD or VSS
--
0.1
1
A
11a
RPU, RPD RPU, RPD (Note2)
--
17.5
36.5
52.5
k
11b
--
17.5
36.5
52.5
k
MC9S08FL16 Series Data Sheet, Rev. 2 12 Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C 12 13 14 15 16 DC injection C current 3, 4,
5
Characteristic Single pin limit Total MCU limit, includes sum of all stressed pins
Symbol IIC CIn VRAM VPOR tPOR VLVD1
Condition VIN < VSS, VIN > VDD -- -- -- --
Min. -0.2 -5 -- -- 0.9 10
Typical1 -- -- -- 0.6 1.4 --
Max. 0.2 5 8 1.0 2.0 --
Unit mA mA pF V V s
C Input capacitance, all pins C RAM retention voltage C POR re-arm voltage D POR re-arm time Low-voltage detection threshold -- high range P VDD falling VDD rising Low-voltage detection threshold -- low range P VDD falling VDD rising Low-voltage warning threshold -- high range 1 C VDD falling VDD rising Low-voltage warning threshold -- high range 0 P VDD falling VDD rising Low-voltage warning threshold low range 1 P VDD falling VDD rising Low-voltage warning threshold -- low range 0 C VDD falling VDD rising C Low-voltage inhibit reset/recover hysteresis
6
--
17
3.9 4.0
4.0 4.1
4.1 4.2
V
VLVD0
--
2.48 2.54
2.56 2.62
2.64 2.70
V
VLVW3
--
18
4.5 4.6
4.6 4.7
4.7 4.8
V
VLVW2
--
4.2 4.3
4.3 4.4
4.4 4.5
V
VLVW1
--
19
2.84 2.90
2.92 2.98
3.00 3.06
V
VLVW0
--
2.66 2.72 -- --
2.74 2.80 100 1.21
2.82 2.88 -- --
V
20 21
1 2 3 4 5
Vhys VBG
-- --
mV V
C Bandgap voltage reference7
6 7
Typical values are measured at 25 C. Characterized, not tested. The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when measured externally on the pin. All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. Factory trimmed at VDD = 5.0 V, Temp = 25 C
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 13
Electrical Characteristics
Typical IOH vs. VDD-VOH VDD = 5 V (High Drive)
50.000 45.000 40.000 35.000 30.000 mA 25.000 20.000 15.000 10.000 5.000 0.000 0 0.3 0.5 0.8 V
Figure 6. Typical IOH Vs VDD-VOH (VDD = 5.0 V) (High Drive)
-40C 0C 25C 55C 85C
1
1.3
2
MC9S08FL16 Series Data Sheet, Rev. 2 14 Freescale Semiconductor
Electrical Characteristics
Typical IOH vs. VDD-VOH VDD = 5V (Low Drive)
10.000 9.000 8.000 7.000 6.000 mA 5.000 4.000 3.000 2.000 1.000 0.000 0 0.3 0.5 0.8 V 1 1.3 2 -40C 0C 25C 55C 85C
Figure 7. Typical IOH Vs VDD-VOH (VDD = 5.0 V) (Low Drive)
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 15
Electrical Characteristics
Typical IOL vs. VOL VDD = 5 V (High Drive)
50.000 45.000 40.000 35.000 30.000 mA 25.000 20.000 15.000 10.000 5.000 0.000 0 0.3 0.5 0.8 V 1 1.3 2 -40C 0C 25C 55C 85C
Figure 8. Typical IOH Vs VOL (VDD = 5.0 V) (High Drive)
MC9S08FL16 Series Data Sheet, Rev. 2 16 Freescale Semiconductor
Electrical Characteristics
Typical IOL vs. VOL VDD = 5V (Low Drive)
14.000 12.000 10.000 -40C 8.000 mA 6.000 4.000 2.000 0.000 0 0.3 0.5 0.8 V 1 1.3 2 0C 25C 55C 85C
Figure 9. Typical IOH Vs VOL (VDD = 5.0 V) (Low Drive)
5.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 17
Electrical Characteristics
Table 8. Supply Current Characteristics
Num C Parameter Symbol Bus Freq 10 MHz Run supply current FEI mode, all modules off P RIDD 1 MHz 5 VDD (V) Typical1 5.66 5.75 5.80 1.61 1.65 1.78 2.79 2.86 2.88 5 1 MHz Stop2 mode supply current Stop3 mode supply current no clocks active ADC adder to stop3 ICS adder to stop3 EREFSTEN = 1 LVD adder to stop3 S2IDD S3IDD -- -- -- -- -- -- -- -- 5 5 5 5 5 1.05 1.06 1.06 1.06 1.17 163.88 1.25 161.3 Max Unit Temp -40 C 25 C 85 C mA -- -40 C 25 C 85 C -40 C 25 C 85 C -40 C 25 C 85 C A A A A A -40 to 85 C -40 to 85 C 25 C 25 C 25 C
P 1
--
C 2 C C 3 4 5 6
1
10 MHz Wait mode supply current FEI mode, all modules off WIDD
-- A -- -- -- -- -- --
C C C C
Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value.
MC9S08FL16 Series Data Sheet, Rev. 2 18 Freescale Semiconductor
Electrical Characteristics
5.8
External Oscillator (XOSC) and ICS Characteristics
Table 9. XOSC and ICS Specifications (Temperature Range = -40 to 85 C Ambient)
Refer to Figure 11 for crystal or resonator circuits.
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1) FEE or FBE mode2 C High range (RANGE = 1), high gain (HGO = 1), FBELP mode High range (RANGE = 1), low power (HGO = 0), FBELP mode D Load capacitors Feedback resistor Low range (32 kHz to 38.4 kHz) High range (1 MHz to 16 MHz)
flo fhi fhi fhi C1 C2
32 1 1 1
-- -- -- --
38.4 5 16 8
kHz MHz MHz MHz
2
See Note3
3
D
RF
10 1
M M
4
D
Series resistor -- Low range Low gain (HGO = 0) High gain (HGO = 1)
RS
-- --
0 100
-- --
k
5
Series resistor -- High range Low Gain (HGO = 0) High Gain (HGO = 1) D 8 MHz 4 MHz 1 MHz Crystal startup time4, 5 Low range, low power Low range, high power C High range, low power High range, high power T Internal reference start-up time Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) D FEE or FBE mode2 FBELP mode P Average internal reference frequency -- trimmed
6 P DCO output frequency range -- trimmed Low range (DRS = 00)
RS
-- -- -- -- -- -- -- --
0 0 0 200 400 5 15 60
0 10 20 -- -- -- -- 100
k
6
t CSTL t CSTH
ms
7
tIRST
s
8
fextal
0.03125 0 -- 16
-- -- 31.25 --
5 20 -- 20
MHz MHz kHz MHz
9 10
fint_t fdco_t
11
C
Total deviation of DCO output from trimmed frequency4 Over full voltage and temperature range Over fixed voltage and temperature range of 0 to 70C
fdco_t tAcquire
--
-1.0 to 0.5 0.5
2 1 1
%fdco ms
12
C FLL acquisition time4,7
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 19
Electrical Characteristics
Table 9. XOSC and ICS Specifications (Temperature Range = -40 to 85 C Ambient) (continued)
Num 13
1 2 3 4 5 6 7
C C
Characteristic Long term jitter of DCO output clock (averaged over 2 ms interval) 8
Symbol CJitter
Min --
Typical1 0.02
Max 0.2
Unit %fdco
8
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. See crystal or resonator manufacturer's recommendation. This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
XOSC EXTAL XTAL RS
RF
C1
Crystal or Resonator C2
Figure 10. Typical Crystal or Resonator Circuit
MC9S08FL16 Series Data Sheet, Rev. 2 20 Freescale Semiconductor
Electrical Characteristics
1.00%
0.50%
0.00% Deviation (%) -60 -40 -20 -0.50% 0 20 40 60 80 100 120
-1.00%
TBD
Temperature
-1.50%
-2.00%
Figure 11. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)
5.9
AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 21
Electrical Characteristics
5.9.1
Num 1 2 3 4 5 6 C D D D D D D
Control Timing
Table 10. Control Timing
Rating Bus frequency (tcyc = 1/fBus) Internal low power oscillator period External reset pulse width2 Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time -- Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Symbol fBus tLPO textrst trstdrv tMSSU tMSH Min dc 700 100 34 x tcyc 500 100 Typical1 -- -- -- -- -- -- Max 10 1300 -- -- -- -- Unit MHz s ns ns ns s
7
D
tILIH, tIHIL
100 1.5 x tcyc 100 1.5 x tcyc
-- -- -- --
-- -- -- --
ns
8
D
tILIH, tIHIL
ns
tRise, tFall
-- --
16 23
-- --
ns
9
C
Port rise and fall time -- High output drive (PTxDS = 1) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
1 2
tRise, tFall
-- --
5 9
-- --
ns
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40 C to 85 C.
textrst RESET PIN
Figure 12. Reset Timing
MC9S08FL16 Series Data Sheet, Rev. 2 22 Freescale Semiconductor
Electrical Characteristics
tIHIL KBIPx
IRQ/KBIPx tILIH
Figure 13. IRQ/KBIPx Timing
5.9.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 11. TPM Input Timing
No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min 0 4 1.5 1.5 1.5 Max fBus/4 -- -- -- -- Unit Hz tcyc tcyc tcyc tcyc
tTCLK tclkh
TCLK tclkl
Figure 14. Timer External Clock
tICPW TPMCHn
TPMCHn tICPW
Figure 15. Timer Input Capture Pulse
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 23
Electrical Characteristics
5.10
ADC Characteristics
Table 12. 8-Bit ADC Operating Conditions
Conditions Absolute Symb VDDA
2
Characteristic Supply voltage
Min 4.5 -100 -100 VREFL -- -- -- 0.4
Typical1 -- 0 0 -- 4.5 3 -- -- --
Max 5.5 100 100 VREFH 5.5 5 10 8.0
Unit V mV mV V pF k k
Comment
Delta to VDD (VDD - VDDA) Ground voltage Input voltage Input capacitance Input resistance Analog source resistance Delta to VSS (VSS - VSSA) -- -- --
VDDA VSSA VADIN CADIN RADIN RAS fADCK
2
8-bit mode (all valid fADCK)
External to MCU
ADC conversion High speed (ADLPC = 0) clock frequency Low power (ADLPC = 1)
1
MHz 0.4 4.0
Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK= 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+ -
+ -
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 16. ADC Input Impedance Equivalency Diagram
MC9S08FL16 Series Data Sheet, Rev. 2 24 Freescale Semiconductor
Electrical Characteristics
Table 13. 8-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
C Characteristic Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Supply Current ADLPC=1 ADLSMP=0 ADCO=1 Supply Current ADLPC=0 ADLSMP=1 ADCO=1 Supply Current ADLPC=0 ADLSMP=0 ADCO=1 Supply Current ADC Asynchronous Clock Source Conversion Time (Including sample time) Sample Time Long Sample (ADLSMP = 1) D Temp Sensor Slope Temp Sensor Voltage Total Unadjusted Error Differential Non-Linearity Integral Non-Linearity Zero-Scale Error Full-Scale Error -40C- 25C m 25C- 125C 25 C VTEMP25 -- -- 3.638 1.396 -- -- mV Includes quantization Stop, Reset, Module Off High Speed (ADLPC = 0) Low Power (ADLPC = 1) Short Sample (ADLSMP = 0) Long Sample (ADLSMP = 1) Short Sample (ADLSMP = 0) P tADS tADC fADACK Conditions Symb Min Typ1 Max Unit Comment
T
IDDA
--
133
--
A
T
IDDA
--
218
--
A
T
IDDA
--
327
--
A
P
IDDA
--
0.582
1
mA
C P
IDDA
-- 2 1.25 -- -- -- -- --
0.011 3.3 2 20 40 3.5 23.5 3.266
1 5
A MHz tADACK = 1/fADACK
3.3 -- -- -- -- -- mV/C ADCK cycles ADCK cycles
P
See reference manual for conversion time variances
D
P
8-bit mode
ETUE
--
0.5
1.0
LSB2
P T P T
8-bit mode3 8-bit mode 8-bit mode 8-bit mode
DNL INL EZS EFS
-- -- -- --
0.3 0.3 0.5 0.5
0.5 0.5 0.5 0.5
LSB2 LSB2 LSB2 LSB2 VADIN = VSSA VADIN = VDDA
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 25
Electrical Characteristics
Table 13. 8-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
C D Characteristic Quantization Error Input Leakage Error Conditions 8-bit mode Symb EQ EIL Min -- Typ1 -- 0.1 Max 0.5 1 Unit LSB2 LSB2 Pad leakage2 * RAS Comment
D
1
8-bit mode
--
Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 Based on input pad leakage current. Refer to pad electricals.
5.11
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section.
Table 14. Flash Characteristics
C D D D D P P P P Characteristic Supply voltage for program/erase -40 C to 85 C Supply voltage for read operation Internal FCLK frequency
1
Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass RIDDBP RIDDPE
Min 4.5 4.5 150 5
Typical -- -- -- -- 9 4 4000 20,000
Max 5.5 5.5 200 6.67
Unit V V kHz s tFcyc tFcyc tFcyc tFcyc
Internal FCLK period (1/FCLK) Byte program time (random Byte program time (burst Page erase Mass erase time2 time2 current3
4
location)2
mode)2
Byte program Page erase C C
1 2
-- -- --
4 6 10,000 100
-- -- -- --
mA mA cycles years
current3
Program/erase endurance TL to TH = -40 C to 85 C T = 25 C Data retention5 tD_ret
5
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures DD with VDD = 5.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
MC9S08FL16 Series Data Sheet, Rev. 2 26 Freescale Semiconductor
Ordering Information
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
5.12
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
5.12.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (the North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels.
Table 15. Radiated Emissions, Electric Field
Parameter Radiated emissions, electric field Symbol VRE_TEM Conditions VDD = 5.0 V TA = 25 C package type 32-pin LQFP Frequency 0.15 - 50 MHz 50 - 150 MHz 150 - 500 MHz 500 - 1000 MHz IEC Level SAE Level
1
fOSC/fBUS 4 MHz crystal 19 MHz bus
Level1 (Max) 9 5 2 1 N 1
Unit dBV
-- --
Data based on qualification test results.
6
Ordering Information
Table 16. Device Numbering System
Device Number1 FLASH MC9S08FL16 MC9S08FL8 16 KB 8 KB Memory RAM 1024 768 32 SDIP 32 LQFP Available Packages2
This section contains ordering information for MC9S08FL16 series devices. See below for an example of the device numbering system.
MC9S08FL16 Series Data Sheet, Rev. 2 Freescale Semiconductor 27
Package Information
1
See the reference manual, MC9S08FL16 Series Reference Manual, for a complete description of modules included on each device. 2 See Table 17 for package information.
Example of the device numbering system:
MC 9 S08 FL 16 Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family C XX
Package designator (see Table 17) Temperature range (C =-40 C to 85 C) Approximate flash size in KB
7
Package Information
Table 17. Package Descriptions
Pin Count 32 32 Package Type Low Quad Flat Package Shrink Dual In-line Package Abbreviation LQFP SDIP Designator LC BM Case No. 873A-03 1376-02 Document No. 98ASH70029A 98ASA99330D
7.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 17.
MC9S08FL16 Series Data Sheet, Rev. 2 28 Freescale Semiconductor
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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2009. All rights reserved. MC9S08FL16 Rev. 2 7/2009

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